The present general inventive concept relates to gate arrays and, more particularly, to a switch block circuit in a field programmable gate array.
In general, a field programmable gate array (hereinafter referred to as “FPGA”) is a chip which allows a user to implement desired integrated circuits using several hundreds of switches.
A switch block is a set of switches and may be divided into blocks that are capable of connecting input, output, and routing tracks.
A switch is functionally a static random access memory (SRAM), but has the form of a latch or flip-flop in practical circuit implementation because it should be accessed by each single bit. For this reason, the switch requires a larger silicon area than a conventional memory such as an SRAM or DRAM.
In the design of an FPGA, it is the most significant to maximize a gate that a user can use. This is accomplished by minimizing an occupied silicon area while increasing programmability.
One of methods for decreasing the number of switches is to optimize a switch block according to the kind of an integrated circuit implemented in an FPGA. That is, all possible pattern connections can be made available in a control-oriented circuit, and a bit-slice pattern connection can be made available in a data-pass-oriented circuit. The optimization of the switch block makes it possible to implement a switch block including a much smaller number of switches.
Nonetheless, it is difficult to apply a switch block for use in a data-pass-oriented circuit to the cases except for a data pass circuit. In the case that a switch block for use in data-pass-oriented circuit is used in a control-oriented circuit, additional tracks are assigned to a control-oriented switch block. Since the additional tracks are required, use efficiency of the switch block is reduced.